Embodiments of the present invention relate to processor-based systems, and more particularly to implementation of a memory coherency protocol within such a system.
In recent years, processors have incorporated increasing support for thread-level parallelism. Usually, the thread-level parallelism exploited by architectures is explicit or non-speculative. The use of speculative thread-level parallelism has been proposed to further increase the benefits of multithreaded/multicore architectures. In such approaches, code is partitioned into pieces that are speculatively executed in parallel. Transactional memory execution is a similar technique where different threads are allowed to speculatively access and write to memory, ignoring possible inter-thread data dependencies. On these two execution models, the speculative memory state is atomically committed to the architectural state or discarded depending on run-time checks (e.g., inter-thread memory dependencies).
To efficiently implement these execution models on current multithreaded and multicore processors, hardware support in the memory subsystem is extended with support to manage speculative state, detect inter-thread data dependencies, and commit or squash the speculative state. In this way a memory subsystem may be able to keep a different speculative version per thread of the same memory location so that speculative threads of the same application can share the memory space and write to the same memory locations. A memory subsystem extended with speculation and multi-versioning support is called a multi-version cache (MVC). Often such systems include centralized tables such as a memory disambiguation table to maintain track of speculatively accessed data. However, such hardware support is expensive and consumes significant real estate and power. Such support typically further requires hardware-based read ordering support. Furthermore, significant communication between various caches of such systems is required, including transmission of the speculative data itself, which increases bus traffic and adversely affects performance and power consumption.